如何解决SystemVerilog $ fdisplay将不会打印看起来像格式说明符的字符串
我维护了SystemVerilog库,并且在使用此代码的3年中从未遇到过此问题。 我只能假设用户正在使用某些特殊版本的VCS进行编译/运行。
Compiler version L-2016.06-SP2-7_Full64; Runtime version L-2016.06-SP2-7_Full64
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OVM-2.1.2
和确切的错误:
Error-[STASKE_NEAFFS] Insufficient number of arguments
my_model/my_source_file.sv,659
Number of arguments (2) passed to substitute format specifiers in the string
are less than the number of format specifiers.
Please check the call stack shown above and pass number of arguments equal
to number of format specifiers.
有没有办法强制$fdisplay
打印,即使某些格式说明符未“填写”?
还是通过某种方式告诉VCS忽略此类问题?
目前,我唯一的调试方法是尝试添加相同字符串的$display
,以查看是否发现了任何内容。
这是为UVM编写的非常相似的代码段。对于内部开发的OVM RAL层,实际出错的代码也是如此。即将结束时,对$fdisplay
的调用是发生错误的等效行:
task save_uvm_accesses();
uvm_reg_block model_reg_blocks[$];
uvm_reg regs_of_block[$];
uvm_reg_field fields_of_reg[$];
uvm_reg sub_block;
uvm_reg_file uvm_file;
uvm_reg_backdoor backdoor_access;
uvm_reg_frontdoor front_access;
int fd;
string output_file_name = "UVM_info.csv";
string current_line="";
string frontdoors = "";
string fieldnames = "";
reg_model.get_blocks(model_reg_blocks);
fd = $fopen({output_file_name},"w");
$fdisplay(fd,"reg_name,reg_full_name,unique_file_name,reg_file,backdoor_access,front_access,access methods,fieldnames");
$display("**************** UVM dump regs *******************");
// go through each sub-block
foreach (model_reg_blocks[sub_block]) begin
// go through each reg in sub-block
regs_of_block = {};
model_reg_blocks[sub_block].get_registers(regs_of_block);
foreach (regs_of_block[rreg]) begin
uvm_reg_map reg_map[$];
frontdoors = "\"";
fieldnames = "\"";
fields_of_reg = {};
current_line ="";
uvm_file = regs_of_block[rreg].get_regfile();
regs_of_block[rreg].get_maps(reg_map);
//backdoor_access = regs_of_block[rreg].get_backdoor(1);
backdoor_access = model_reg_blocks[sub_block].get_backdoor(1);
// enumerate any available frontdoor accesses
foreach (reg_map[map]) begin
front_access = regs_of_block[rreg].get_frontdoor(reg_map[map]);
if(front_access != null)
frontdoors = {frontdoors,$sformatf("%s,",front_access.get_name())};
end
frontdoors = {frontdoors,"\""};
regs_of_block[rreg].get_fields(fields_of_reg);
foreach (fields_of_reg[current_fieldname]) begin
fieldnames = {fieldnames,fields_of_reg[current_fieldname].get_name())};
end
fieldnames = {fieldnames,"\""};
// current_line = {current_line,rreg}; r
current_line = {current_line,regs_of_block[rreg].get_name())};
current_line = {current_line,regs_of_block[rreg].get_full_name())};
current_line = {current_line,model_reg_blocks[sub_block].get_name())};
if(uvm_file == null)
current_line = {current_line,"null,"};
else
current_line = {current_line,uvm_file.get_name())};
if(backdoor_access == null)
current_line = {current_line,backdoor_access.get_name())};
current_line = {current_line,frontdoors)};
current_line = {current_line,"backdoor,"};
current_line = {current_line,fieldnames};
$fdisplay(fd,current_line);
end
end
$fclose(fd);
endtask: save_uvm_accesses
解决方法
我最终只是从以下更改了最后的fdisplay行:
$fdisplay(fd,current_line);
到
$fdisplay(fd,"%s",current_line);
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