我在verilog中获得了此shifter模块的未知值

如何解决我在verilog中获得了此shifter模块的未知值

我正在尝试使用32 mux32实现32位右移。我的mux32工作正常，但是当我尝试一些测试用例时，此模块仍返回未知值。我真的不知道问题是什么。如果您能帮助我，我将不胜感激。 请帮忙！！！谢谢。下面是我编写的模块代码。

module shiftbitright(c,a,b);
output [31:0]c;
input [31:0]a;
input [4:0]b;
wire [31:0]d=32'b0;
genvar i;
generate for( i=0; i<1; i=i+1) begin:bit assign d[i]=a[31-i]; end endgenerate
mux32 m1(d,b,c[31]);
generate for( i=0; i<2; i=i+1) begin:bit1 assign d[i]=a[31-i]; end endgenerate
mux32 m2(d,c[30]);
generate for( i=0; i<3; i=i+1) begin:bit2 assign d[i]=a[31-i]; end endgenerate
mux32 m3(d,c[29]);
generate for( i=0; i<4; i=i+1) begin:bit3 assign d[i]=a[31-i]; end endgenerate
mux32 m4(d,c[28]);
generate for( i=0; i<5; i=i+1) begin:bit4 assign d[i]=a[31-i]; end endgenerate
mux32 m5(d,c[27]);
generate for( i=0; i<6; i=i+1) begin:bit5 assign d[i]=a[31-i]; end endgenerate
mux32 m6(d,c[26]);
generate for( i=0; i<7; i=i+1) begin:bit6 assign d[i]=a[31-i]; end endgenerate
mux32 m7(d,c[25]);
generate for( i=0; i<8; i=i+1) begin:bit7 assign d[i]=a[31-i]; end endgenerate
mux32 m8(d,c[24]);
generate for( i=0; i<9; i=i+1) begin:bit8 assign d[i]=a[31-i]; end endgenerate
mux32 m9(d,c[23]);
generate for( i=0; i<10; i=i+1) begin:bit9 assign d[i]=a[31-i];end  endgenerate
mux32 m10(d,c[22]);
generate for( i=0; i<11; i=i+1) begin:bit10 assign d[i]=a[31-i];end  endgenerate
mux32 m11(d,c[21]);
generate for( i=0; i<12; i=i+1) begin:bit11 assign d[i]=a[31-i];end  endgenerate
mux32 m12(d,c[20]);
generate for( i=0; i<13; i=i+1) begin:bit12 assign d[i]=a[31-i];end  endgenerate
mux32 m13(d,c[19]);
generate for( i=0; i<14; i=i+1) begin:bit13 assign d[i]=a[31-i];end  endgenerate
mux32 m14(d,c[18]);
generate for( i=0; i<15; i=i+1) begin:bit14 assign d[i]=a[31-i];end  endgenerate
mux32 m15(d,c[17]);
generate for( i=0; i<16; i=i+1) begin:bit15 assign d[i]=a[31-i];end  endgenerate
mux32 m16(d,c[16]);
generate for( i=0; i<17; i=i+1) begin:bit16 assign d[i]=a[31-i];end  endgenerate
mux32 m17(d,c[15]);
generate for( i=0; i<18; i=i+1) begin:bit17 assign d[i]=a[31-i];end  endgenerate
mux32 m18(d,c[14]);
generate for( i=0; i<19; i=i+1) begin:bit18 assign d[i]=a[31-i];end  endgenerate
mux32 m19(d,c[13]);
generate for( i=0; i<20; i=i+1) begin:bit19 assign d[i]=a[31-i];end  endgenerate
mux32 m20(d,c[12]);
generate for( i=0; i<21; i=i+1) begin:bit20 assign d[i]=a[31-i];end  endgenerate
mux32 m21(d,c[11]);
generate for( i=0; i<22; i=i+1) begin:bit21 assign d[i]=a[31-i];end  endgenerate
mux32 m22(d,c[10]);
generate for( i=0; i<23; i=i+1) begin:bit22 assign d[i]=a[31-i];end  endgenerate
mux32 m23(d,c[9]);
generate for( i=0; i<24; i=i+1) begin:bit23 assign d[i]=a[31-i];end  endgenerate
mux32 m24(d,c[8]);
generate for( i=0; i<25; i=i+1) begin:bit24 assign d[i]=a[31-i];end  endgenerate
mux32 m25(d,c[7]);
generate for( i=0; i<26; i=i+1) begin:bit25 assign d[i]=a[31-i];end  endgenerate
mux32 m26(d,c[6]);
generate for( i=0; i<27; i=i+1) begin:bit26 assign d[i]=a[31-i];end  endgenerate
mux32 m27(d,c[5]);
generate for( i=0; i<28; i=i+1) begin:bit27 assign d[i]=a[31-i];end  endgenerate
mux32 m28(d,c[4]);
generate for( i=0; i<29; i=i+1) begin:bit28 assign d[i]=a[31-i];end  endgenerate
mux32 m29(d,c[3]);
generate for( i=0; i<30; i=i+1) begin:bit29 assign d[i]=a[31-i];end  endgenerate
mux32 m30(d,c[2]);
generate for( i=0; i<31; i=i+1) begin:bit30 assign d[i]=a[31-i];end  endgenerate
mux32 m31(d,c[1]);
generate for( i=0; i<32; i=i+1) begin:bit31 assign d[i]=a[31-i];end  endgenerate
mux32 m32(d,c[0]);
endmodule

我的测试台

`timescale 10ns/1ns
module shiftbitright_tb;
wire [31:0]c;
reg [31:0]a;
reg [4:0]b;
shiftbitright s1(.c(c),.a(a),.b(b));
initial begin
$monitor("a=%h b=%b c=%h",c);
a=32'hff000000;
b=5'd1;
#50
a=32'hf00f0000;
b=5'd8;
end
endmodule