主/从 JK 触发器 (GHDL) 中的“未解析信号的几个来源”

如何解决主/从 JK 触发器 (GHDL) 中的“未解析信号的几个来源”

我正在尝试使用基于 GHDL 中的 NAND 逻辑的两个 CLK SR 触发器组件来实现一个 clk 主/从 JK 触发器。

我偶然发现了以下错误：

• 未解析信号的几个来源
• 细化过程中的错误

我知道，事实上，问题出在从锁存输入 SR（S

我尝试以多种方式初始化这些值，但未能通过该错误。

非常感谢您能提供的任何帮助。

enter image description here

JK FF 组件：

library ieee;
use ieee.std_logic_1164.all;

entity jkff_ms is
    port
    (
        J,K,clk : in std_ulogic;
        Q,nQ : inout std_ulogic
    );
end entity;

architecture behave of jkff_ms is
    component srff
        port
        (
            S,R,clk : in std_ulogic;
            Q,nQ : inout std_ulogic --     Q <= (S nand clk) nand nQ; / nQ <= (R nand clk) nand Q;
        );
    end component;
    
    signal S,SRQ,SRnQ : std_ulogic;
    signal t0,t1,t2,t3,t4 : std_ulogic;
begin
    SRQ <= '1';
    SRnQ <= '0';

    t0 <= clk nand clk; -- NOT
    t1 <= J nand nQ;
        t2 <= t1 nand t1; -- NOT
    t3 <= K nand Q;
        t4 <= t3 nand t3; -- NOT
    
    SR0: srff port map (t2,t4,clk,SRnQ);
    SR1: srff port map (SRQ,SRnQ,t0,Q,nQ);
end architecture; 

JK FF 测试台：

library ieee;
use ieee.std_logic_1164.all;

entity jkff_ms_tb is
end entity;

architecture rtl of jkff_ms_tb is
    procedure clk_gen(signal clk0 : out std_ulogic; constant freq : real) is
        constant T : time := 1000 ms/freq;
        constant ht : time := T/2; -- High_Time
        constant lt : time := T - ht; -- Low_Time
    begin
        assert (ht /= 0 fs) report "clk_plain: High_Time = 0; time resolution to large for freq" severity FAILURE;
        loop
            clk0 <= '1';
            wait for ht;
            clk0 <= '0';
            wait for lt;
        end loop;
    end procedure;
    
    component jkff_ms
        port
        (
            J,nQ : inout std_ulogic
        );
    end component;
    
    signal J,nQ : std_ulogic;
    signal clk_100 : std_ulogic;
begin
    clk_gen(clk_100,100.000e6); -- 100 MHz
    
    assert FALSE report "Time resolution:" & time'image(time'succ(0 fs)) severity NOTE;
    
    JK: jkff_ms port map (J,clk_100,nQ);
    
    process
    begin
        J <= 'X';
        K <= 'X';
        wait for 10 ns;
        
        J <= '0';
        K <= '0';
        wait for 10 ns;
        
        J <= '0';
        K <= '0';
        wait for 10 ns;
        
        J <= '1';
        K <= '0';
        wait for 10 ns;
        
        J <= '0';
        K <= '0';
        wait for 10 ns;
        
        J <= '0';
        K <= '1';
        wait for 10 ns;
        
        J <= '1';
        K <= '0';
        wait for 10 ns;
        
        J <= '0';
        K <= '0';
        wait for 10 ns;     
        
        J <= '0';
        K <= '1';
        wait for 10 ns;
        
        assert false report "End of Test";
        wait;
    end process;
end architecture;